HomeBuisness and financeTSMC is working on 2nm-Chips, Expected to Release by 2025

TSMC is working on 2nm-Chips, Expected to Release by 2025

The performance and efficiency of chipsets depend on the number of transistors they have. To accommodate more transistors on a chip, their size needs to be reduced. This is known as ‘Moore’s Law’, which states the number of transistors on microprocessors should double every two years by decreasing their size. The current-gen best processors are built-on 7nm process, which is expected to be replaced with 5nm later this year. However, even before that, TSMC has now revealed to have started R&D for 2nm chips.

In its recent annual report to shareholders, TSMC has announced that it has kick-started research and development for the 2nm process in 2019 itself. The semiconductor manufacturing company is yet to deliver Apple’s next-gen 5nm mobile chip slated to release in the last quarter of this year.

For context, the 2nm chips will be able to hold 3.5 times more transistors than the now best 7nm chipsets available in the market.

Additionally, it also revealed the roadmap for 3nm chips lask week, which is progressing as planned. The first batch of risk production is expected to begin in 2021, followed by volume production in the second half of 2022.

The only major competitor for TSMC is Samsung, however, it is yet to mass-manufacture 5nm chips and has even delayed 3nm chipsets to 2022 due to COVID-19 pandemic.

Nevertheless, although TSMC has started working on 2nm chips, we won’t be able to see it anytime soon. The earliest we can expect it to be ready for the masses is 2025.

To maintain and strengthen TSMC’s technology -leadership, the Company also plans to continue investing heavily in R&D. For advanced CMOS logic, the Company’s 5nm & 3nm CMOS nodes continue progressing in the pipeline. In addition, the Company’s- reinforced exploratory R&D work is focused on beyond 3nm node; in areas such as 3D transistors, new memory, & low-R interconnect, on track to establish a solid foundation to feed into technology platforms. For 3D IC advanced packaging, innovations for energy efficient sub-system integration and scaling provide further -augmentation to CMOS logic applications-.

For specialty technologies, the Company has also intensified its focus on new specialty technologies such as RF and 3D intelligent sensors targeting 5G & smart IoT applications. The Corporate Research functions established in 2017 continues to focus on novel- materials, process, devices, nanowires, memories, etc. for the long term, beyond 8 to 10 years. The Company as well continues to collaborate with external -research bodies from academia to industry consortias alike with the goal of extending -Moore’s Law & paving the road to future cost effective technologies and manufacturing the solutions for its customers.

With a highly competent and dedicated &D team and its unwavering commitment to innovation, the TSMC is confident in her ability to deliver the best and most cost effective SoC-technologies to its customers and to drive future- business growth and profitability for the years to come.

In nanometers, the difference is small, but we should look at what it means for transistor density. A 7nm chip can fit 2 times more transistors on the same die as a 14nm one, but a 2nm one will be able to fit 3.5 times more than a 7nm one!

Chips that powerful and that energy-efficient will open up a whole new set of functions our phones will be able to perform. And while that future is still a few years away, it’s steadily coming and it’s exciting!


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